Multi-channel digital nuclear instrument system with multiple channel synchronous measurement of nuclear pulse digital processor, each of the digital nuclear pulse processor independent of the wave transmission, forming data transmission, the spectral acquisition and list - mode packet transmission, and other functions, in order to achieve the multi-channel nuclear measurement system and PC, real-time and reliable data transmission, often need to hundreds of megabytes per second transmission speed, the system was designed based on FT601Q start high-speed data communication circuit, multi-channel digital nuclear measurement system controller using FPGA as the main control chip of the whole system, The USB3.0 bridge chip FT601Q introduced by FTDI company is used to realize high-speed data transmission between upper computer and multi-channel digital core measurement system. The high speed USB3.0 data communication design introduced realizes the stable data transmission of up to 360MB/s between the upper computer and the multi-channel digital core measurement system.

In order to achieve the best measurements of different types of nuclear radiation detectors, the multi-channel digital nuclear measurement system has the ability to connect multiple channels of nuclear radiation detectors, including liquid scintillator detectors, plastic scintillator detectors, high purity germanium and lanthanum bromide detectors. The system is an embedded ADC board card with different sampling rates, which adopts modular design and can be measured in any combination.

As the multi-channel digital core measurement system simultaneously controls several embedded ADC board CARDS, in order to realize real-time data processing in the upper computer, the system and the upper computer need to support stable and efficient data transmission. Taking the system working in particle data mode as an example, if the data volume of each channel reaches 500k per second and the size of particle packet is set to 32Byte, then the data volume of six channels acquired each time is 94MByte. With the increase of the number of channels in the data acquisition system and the increase of the data passing rate, the maximum communication speed of the traditional USB2.0 protocol of 480Mbps(60MByte/s) cannot meet the requirements of the system. The maximum transmission rate of USB3.0 protocol is 5.0Gbps(500MByte/s). Therefore, the communication between this system and the upper computer adopts USB3.0 protocol to realize real-time, stable and efficient data transmission of multi-channel digital core measurement system under different data acquisition modes.

At present, most of the U S B 3.0 communication circuits are designed based on the C y U S B 3 0 1 4 (F X 3) chip of C y p r e S S company. This system USES FT601Q, a USB3.0 bridge chip developed by FTDI company. This chip has the characteristics of simple structure, stable operation, low difficulty compared with CYUSB3014 chip development, and fully satisfies the high-speed data transmission of multi-channel digital core measurement system and upper computer in performance.

At present, most of the U S B 3.0 communication circuits are designed based on the C y U S B 3 0 1 4 (F X 3) chip of C y p r e S S company. This system USES FT601Q, a USB3.0 bridge chip developed by FTDI company. This chip has the characteristics of simple structure, stable operation, low difficulty compared with CYUSB3014 chip development, and fully satisfies the high-speed data transmission of multi-channel digital core measurement system and upper computer in performance.

1. Operating principle of the system

Multichannel digital nuclear measurement system.

The multi-channel digital nuclear measurement system consists of six embedded ADC board CARDS, which are connected to the front-end nuclear detector circuit. The measurement data is sent to the baseplate FPGA through the high-speed SPI interface, which is used for data processing and analysis. After marking the channel ID number, FT601Q forwards the data to the topmost machine through the USB3.0 control logic.

2. Data transmission system design

The design of multi-channel digital nuclear measurement transmission system includes FT601Q interface circuit and FPGA master control circuit. Floor master FPGA using ALTERA company Cyclone Ⅳ E series chips, models for EP4CE75F23C8N, used for the front-end data acquisition and preliminary processing, and control the FT601Q, realize communication with PC software.

2.1 interface circuit design

The FT601Q used in the interface circuit design is a bridge chip between the USB3.0 and FIFO of FTDI company, which is compatible with the USB3.0 and USB2.0 interfaces, and supports two parallel communication protocols from FIFO bus. It can work in the "multi-channel FIFO" bus protocol mode and the "245 synchronous FIFO" bus communication protocol mode. It has a built-in 16KB FIFO data cache RAM and a 32-bit parallel FIFO bus interface. Internal structure of FT601Q. Compared with CYPRESS's CYUSB3014 chip integrated with ARM9 kernel, FTDI's FT601Q has enough performance to meet most USB3.0 communication applications and is suitable for this design. Besides, FT601Q is packaged with qfn-76, with simple peripheral circuit structure, which can significantly reduce the plate making process, simplify the system design, and be more widely used. The FT601Q circuit designed in this paper works in the "245 synchronous FIFO" bus communication protocol mode. The 16KB internal FIFO buffer is configured as two 4KB double buffers on RX and TX channels. To ensure the clock frequency of FIFO interface output is 100MHz, the chip power supply voltage is set to 2.5v. USB3.0 communication circuit based on FT601Q.

2.2 FPGA master control circuit design

Main control circuit design of the main control chip of ALTERA company Cyclone EP4CE75F23C8N Ⅳ E series. EP4CE75F23C8N is packaged by fbga-484, with 75408 logic units, 2810880bit memory,293 I/O interfaces, and operating voltage of 1.0v ~ 1.2v. The system fully meets the front-end data acquisition, processing and control requirements of USB3.0 circuit.

The main control circuit USES a 64mbit-sized SPI FLASH chip, model M25P64, which works in the 3.3v-cmos voltage standard. Due to its non-volatile nature, SPI FLASH can be used as the startup image file of FPGA system, including FPGA bit file, soft core application code and other user data files. At the same time, two MICRON mt47h64m16hr-3it DDR2 chips are connected to the master FPGA through the DDR2 interface, with a total capacity of 2Gbit. Two DDR2 chips constitute a 32-bit data bus, which is used for measuring data, caching and reading configuration information.

In order to enable FGPA to work normally, FPGA is provided with 3.3v, 1.8v, 2.5v, 1.2v and VCCIO power on the main control board. The DCDC chip TLV62130RGT from American TI company is adopted for the power supply with large demand for current. It has the characteristics of small volume, small heat, small ripple, large output current and high efficiency.

3 FPGA controller design

The high-speed USB3.0 circuit designed by this system is to transmit the multi-channel, different sampling rate and different working mode data obtained by the multi-channel digital nuclear measurement system to the upper computer software for real-time processing and analysis.

FPGA controller interface logic design includes data acquisition interface logic, DDR2 interface logic and USB3.0 interface logic. The logic of the data acquisition interface is used to connect the embedded ADC board card, and each embedded ADC board card is connected to the backplane FPGA through two groups of high-speed SPI interfaces, which are respectively used for data transmission and parameter configuration of the board card. DDR2 interface logic USES 32-bit parallel data line to connect with external DDR2 memory chip for data cache. USB3.0 interface logic is used to control the data sending and receiving of USB3.0 and connect the FIFO interface of FT601Q. The parameter configuration command sent to the embedded ADC board card by the upper computer is received by the FPGA of the backplane and then sent to the SRAM cache. The configuration information is sent to the embedded ADC board card by the high-speed SPI interface through TX_FIFO. The raw data, filtering and molding data, energy spectrum data and particle data collected by the embedded ADC board card are received by the SPI slave machine, stored in DDR2 SDRAM by RX_FIFO, then read by the master control FPGA, and sent to the upper computer software for processing through the USB3.0 circuit.

USB3.0 logic control state machine structure, FPGA after receiving the command sent by the upper computer to determine the command type. When initializing the system, the FPGA will reply to the information of the front-end embedded ADC board card connected on the baseplate, and correspond to the board card types of each channel, so as to conduct different parameter configuration operations. Under normal working conditions, the upper computer can send parameter configuration command and data acquisition command to the system baseplate. When it is judged as parameter configuration command, the baseboard master control FPGA sends configuration information to the front-end embedded ADC board card through the high-speed SPI interface. When judged as a data acquisition command, the baseplate FPGA obtains data according to different working modes and sends the data to the upper computer software for processing through the USB3.0 interface.

4 test results and analysis

Through the above hardware circuit construction and software design analysis, the Quartus Prime 18.0 of Intel was used to write control code, and the solidified file was generated and downloaded to FPGA. Visual Studio 2015 was used to write the test software of USB3.0 upper computer, and test the data transmission speed and data transceiver of the high-speed USB3.0 communication circuit of the multi-channel digital core measurement system.

4.1 FT601Q communication speed test

After completing the communication circuit hardware design and FPGA program design, the communication speed verification test of FT601Q USB3.0 circuit was conducted through the upper computer software provided by FTDI.

Connect the baseboard circuit of the multi-channel digital core measurement system to the computer through the USB3.0 cable, open the upper computer software provided by FTDI "FT600 Data Streamer DemoApp", and after the driver is installed correctly, the software can recognize the USB3.0 device and display the device information. Test the reading and writing speed results, it can be seen that the data writing speed reaches 368M Byte per second, the data reading speed reaches 352M Byte per second, and the data transmission is stable. In this design, FT601Q works in the communication protocol mode of "245 synchronous FIFO" bus, the clock frequency is 100MHz, the data bit of parallel port is 32 bits, the theoretical communication transmission rate is 400MB/s, while the actual communication speed we tested is 360MB/s, which conforms to the theoretical calculation results.

4.2 transceiver test of multi-channel digital core measurement system

After the FT601Q communication speed test, the data transceiver test was conducted for the multi-channel digital core measurement system. Data acquisition and processing were carried out by FPGA chip on the floor to control FT601Q data sending and receiving. Figure 9 shows the data receiving sequence diagram and data sending sequence diagram obtained by Quartus Prime 18.0 software.

The lanthanum bromide detector is connected to the front end of the multi-parameter system to measure the particle pattern. The detector channel number is selected on the software, and the hardware gain, software gain and time constant value of the embedded board A, D and C card are adjusted in the original waveform mode and the forming waveform mode to ensure the optimal measurement effect. After the configuration is completed, the embedded board card is set to work in the particle mode to obtain the measurement results, including the original spectral line display and the particle data time information and amplitude value information display.

5 conclusion

The test results show that the high-speed transmission system introduced in this paper based on USB3.0 can forward and transmit the data acquired by the multi-channel digital nuclear measurement system at a speed of about 360MB/s, which can meet the working requirements of real-time processing of large amount of data in the system, and the structure is optimized and the work is stable. The multi-channel digital core measurement system works in multi-channel mode, signal direct sampling mode, particle information mode and other modes to carry out waveform transmission, forming data transmission, energy spectrum acquisition and list-mode packet transmission, providing a high-speed, efficient and stable data transmission scheme.